Messages in this thread | | | From | Jesse Barnes <> | Subject | Re: question on memory barrier | Date | Wed, 24 Aug 2005 12:53:53 -0700 |
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On Wednesday, August 24, 2005 12:48 pm, Andy Isaacson wrote: > The first register write will be completed before the second register > write because you use writel, which is defined to have the semantics > you want. (It uses a platform-specific method to guarantee this, > possibly "volatile" or "asm("eieio")" or whatever method your platform > requires.)
writel() ensures ordering? Only from one CPU, another CPU issuing a write at some later time may have its write arrive first. See Documentation/io_ordering.txt for some documentation I put together on this issue.
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