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SubjectRe: question on memory barrier
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On Wed, 24 Aug 2005, Oliver Neukum wrote:

> Am Mittwoch, 24. August 2005 20:22 schrieb linux-os (Dick Johnson):
>>> sorry but I'm not sure to understand you...Do you mean that the first write
>>> into reg_a pointer will be completed before the second write because they're
>>> separated by a (;) ?
>>
>> Yes. The compiler must make sure that every effect of all previous
>> code and all side-effects are complete at a "sequence-point". There
>> are several sequence-points and the most obvious is a ";".
>
> What the compiler may or may not generate is a little beside the point.
> You have no guarantee that the CPU will execute these instructions in
> the order given. If you need ordered writes use the appropriate barriers,
> eg. wmb();

You mean these??

system.h: * For now, "wmb()" doesn't actually do anything, as all
system.h: * Some non intel clones support out of order store. wmb() ceases to be a
system.h:#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
system.h:#define wmb() __asm__ __volatile__ ("": : :"memory")
system.h:#define smp_wmb() wmb()
system.h:#define smp_wmb() barrier()
system.h:#define set_wmb(var, value) do { var = value; wmb(); } while (0)

The "future" black magic that currently does nothing?????

> If this is PCI you also need to worry about the bridge caching. You
> need to do dummy reads.
>

And you never even bothered to read what I said about that???
The write ORDER will NOT change. Period. It's a FIFO. Writes
may be cached for awhile. You can force the writes, IN ORDER,
by doing a dummy read.


Too many people like to pretend that there is some black magic.
It works like it's supposed to. If it doesn't work, you have a bug.


> Regards
> Oliver
>

Cheers,
Dick Johnson
Penguin : Linux version 2.6.12.5 on an i686 machine (5537.79 BogoMips).
Warning : 98.36% of all statistics are fiction.
.
I apologize for the following. I tried to kill it with the above dot :

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