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Hi When we run our application on AMD Opteron processors, we are seeing a large number of L1_AND_L2_DTLB_MISSES. We used oprofile to measure these numbers. We wanted to try with a bigger page size and see if we could bring it down. TLB caches 4k page translations. I don't know if larger page size would even help here. I changed PAGE_SHIFT to 14 ( 16k page size ) in include/asm/page.h and recompiled kernel and modules. It crashed ( PANIC: early exception ) at the very initial stage of loading the image. I looked at some of the mailing list archives for any information on this. I couldn't find anything on this subject . I appreciate any help on this. There seem to be two 2-4MB page translations in L1 TLB cache on AMD machines. Will it be used only when the page size is 2MB or can they be used with smaller page sizes too. Thanks for your help. Regards Subramanyam - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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