Messages in this thread | | | Date | Mon, 27 Jun 2005 09:42:52 +1000 | From | Paul Mackerras <> | Subject | Re: increased translation cache footprint in v2.6 |
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Marcelo Tosatti writes:
> We've noticed a slowdown while moving from v2.4 to v2.6 on a small PPC platform > (855T CPU running at 48Mhz, containing pair of separate I/D TLB caches with > 32 entries each), with a relatively recent kernel (v2.6.11). > > Test in question is a "dd" copying 16MB from /dev/zero to RAMDISK. > > Pinning an 8Mbyte TLB entry at KERNELBASE brought performance back to v2.4 levels.
Why are we not pinning a large TLB entry at KERNELBASE in 2.6? Was that taken out to reduce the size of the tlb miss handler or something?
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