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David Brownell wrote: >>Added EHCI maintainer to this one as well. If possible, this looks like >>a good candidate for a /proc or /sys knob? > > > No, it's based on a mis-understanding of the hardware. > > The controller should only be doing DMA when some driver has submitted > an URB and that URB hasn't yet completed. Pretty much like any other > hardware, like a disk or network controller. Okay, thanks, and okay, crap. Sounded like a nice, plausible explanation... > For periodic transfers -- interrupt, isochronous, neither used for > disk I/O -- the driver issuing the transfer always has control over > the polling period. But that's mostly related to the USB activity; > if a periodic transfer is active, then the current segment of the > periodic schedule has to be scanned (by DMA) every microframe (8x/msec). > If that segment is empty, that's just one word (32 bits). If there > are transfers, it's got to read them and maybe perform them. I see. Well, sort of at least. "Even if the HDD were using periodic transfers, which it isn't, it would be DMAing 32-bits 8x per msec while idle, which certainly isn't going to cost 8MB/s bus bandwidth". Right? Rene. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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