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Dave Jones wrote: > > > > Drop the vendor check; PAT is a generic x86 feature. If AMD is not > > compatible (see below), then use X86_VENDOR_AMD: and default:. > > Done. Does transmeta have PAT btw ? I know newer VIA has it, > but I haven't looked through the docs to double check its > implementation yet. > The Efficeon (TM8xxx) series does have PAT. > > > >+ * Note: On Athlon cpus PAT2/PAT3 & PAT6/PAT7 are both Uncacheable since > > >+ * there is no uncached type. > > If one sets the PAT to "uncached", does one get the same function as > > "uncachable"? > > AIUI, only as long as we don't have an MTRR covering the same range marked WC. > It seems to be the only thing I could find documenting the differences > between 'uncached' and 'uncacheable' in this context. > Though I've only looked through the Intel & AMD K8 docs, I don't have > the K7 ones to hand. > I mean, on the Athlon series, is it really necessary to use a different value? -hpa - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||
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