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Roland Dreier got this right. The purpose of the mmiowb is to ensure that writes to I/O devices while holding a spinlock are ordered with respect to writes issued after the original processor releases and a second processor acquires said spinlock. A MMIO read would be sufficient, but is much heavier weight. On the SGI MIPS-based systems, the "sync" instruction was used. On the Altix systems, a register on the hub chip is read. From comments by jejb, we're looking at modifying the mmiowb API by adding an argument which would be a register to read from if the architecture in question needs ordering in this way but does not have a lighter weight mechanism like the Altix mmiowb. Since there will now need to be a width indication, mmiowb will be replaced with mmiowb[bwlq]. jeremy - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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