Messages in this thread | | | Date | Mon, 14 Nov 2005 13:08:07 +0100 | From | Pavel Machek <> | Subject | Re: latest mtd changes broke collie |
| |
Hi!
> >[Plus I get a warning from jffs2 that flashsize is not aligned to > >erasesize. Then I get lot of messages that empty flash at XXX ends at > >XXX.] > > The datasheet ref'ed earlier says the chips have a 64KB erase block > size, and the sharp driver multiplies that value by an interleave of 4 > chips to set the erase size. What erase size is set under the new
I'm currently using:
{ .mfr_id = 0x00b0, .dev_id = 0x00b0, .name = "Collie hack", .uaddr = { [0] = MTD_UADDR_UNNECESSARY, /* x8 */ }, .DevSize = SIZE_4MiB, .CmdSet = P_ID_INTEL_STD, .NumEraseRegions= 1, .regions = { ERASEINFO(0x10000,64), } },
...so I should use ERASEINFO(0x40000,16)?
> setup? cat /proc/mtd or set loglevel for KERN_DEBUG at chip probe time. > The new code is setting it based on what was read from the CFI query > info reported by the chip times the interleave factor (which apparently > should be set as 4 after detecting 4 chips if CONFIG_MTD_CFI_I4=y).
I do not have collie with me right now. Pavel -- Thanks, Sharp! - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |