Messages in this thread | | | Date | Mon, 03 Oct 2005 08:40:19 -0700 | From | David Brownell <> | Subject | Re: [RFC][PATCH] SPI subsystem |
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> I believe the issue is that you can't properly control the alignment > to ensure that you don't inadvertantly dirty the cache lines > corresponding with the memory you're performing DMA to/from.
That's a much better (== content-ful) explanation; thanks Russell.
Cache line sharing can indeed be a PITA ... and while it's an issue that's not unique to DMA from the stack, it's something that's less manageable there. Plus, DMA isn't always cache-coherent. Meaning that for example DMA to the stack might bypass the cache and then later be overwritten by flushing cached stack updates. (etc.)
- Dave
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