Messages in this thread |  | | | Date | Fri, 14 Jan 2005 08:57:46 -0800 (PST) | | From | Christoph Lameter <> | | Subject | Re: page table lock patch V15 [0/7]: overview II |
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On Fri, 14 Jan 2005, Andi Kleen wrote:
> > Are you sure the cmpxchg8b need a lock prefix? Sure it does to > > If you want it to be atomic on SMP then yes. > > > get the proper "atomic cmpxchg" semantics, but what about a > > simple 64-bit store... If it boils down to 8 byte load, 8 byte > > A 64bit store with a 64bit store instruction is atomic. But > to do that on 32bit x86 you need SSE/MMX (not an option in the kernel) > or cmpxchg8 > > > store on the memory bus, and that store is atomic, then maybe > > a lock isn't needed at all? > > More complex operations than store or load are not atomic without > LOCK (and not all operations can have a lock prefix). There are a few > instructions with implicit lock. If you want the gory details read > chapter 7 in the IA32 Software Developer's Manual Volume 3.
It needs a lock prefix. Volume 2 of the IA32 manual states on page 150 regarding cmpxchg (Note that the atomicity mentioned here seems to apply to the complete instruction not the 64 bit fetches and stores):
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back ifthe comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.) - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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