Messages in this thread Patch in this message |  | | | Date | Thu, 30 Sep 2004 00:15:41 -0700 | | From | Jeremy Higdon <> | | Subject | Re: [PATCH] I/O space write barrier |
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Here's the qla1280 patch to go with Jesse's mmiowb patch. Comments are verbose to satisfy a request from Mr. Bottomley.
signed-off-by: Jeremy Higdon <jeremy@sgi.com>
===== drivers/scsi/qla1280.c 1.65 vs edited ===== --- 1.65/drivers/scsi/qla1280.c 2004-07-28 20:59:10 -07:00 +++ edited/drivers/scsi/qla1280.c 2004-09-29 23:43:30 -07:00 @@ -3397,8 +3397,22 @@ "qla1280_64bit_start_scsi: Wakeup RISC for pending command\n"); sp->flags |= SRB_SENT; ha->actthreads++; + + /* + * Update request index to mailbox4 (Request Queue In). + * The mmiowb() ensures that this write is ordered with writes by other + * CPUs. Without the mmiowb(), it is possible for the following: + * CPUA posts write of index 5 to mailbox4 + * CPUA releases host lock + * CPUB acquires host lock + * CPUB posts write of index 6 to mailbox4 + * On PCI bus, order reverses and write of 6 posts, then index 5, + * causing chip to issue full queue of stale commands + * The mmiowb() prevents future writes from crossing the barrier. + * See Documentation/DocBook/deviceiobook.tmpl for more information. + */ WRT_REG_WORD(®->mailbox4, ha->req_ring_index); - (void) RD_REG_WORD(®->mailbox4); /* PCI posted write flush */ + mmiowb(); out: if (status) @@ -3665,8 +3679,22 @@ "for pending command\n"); sp->flags |= SRB_SENT; ha->actthreads++; + + /* + * Update request index to mailbox4 (Request Queue In). + * The mmiowb() ensures that this write is ordered with writes by other + * CPUs. Without the mmiowb(), it is possible for the following: + * CPUA posts write of index 5 to mailbox4 + * CPUA releases host lock + * CPUB acquires host lock + * CPUB posts write of index 6 to mailbox4 + * On PCI bus, order reverses and write of 6 posts, then index 5, + * causing chip to issue full queue of stale commands + * The mmiowb() prevents future writes from crossing the barrier. + * See Documentation/DocBook/deviceiobook.tmpl for more information. + */ WRT_REG_WORD(®->mailbox4, ha->req_ring_index); - (void) RD_REG_WORD(®->mailbox4); /* PCI posted write flush */ + mmiowb(); out: if (status) @@ -3776,9 +3804,21 @@ } else ha->request_ring_ptr++; - /* Set chip new ring index. */ + /* + * Update request index to mailbox4 (Request Queue In). + * The mmiowb() ensures that this write is ordered with writes by other + * CPUs. Without the mmiowb(), it is possible for the following: + * CPUA posts write of index 5 to mailbox4 + * CPUA releases host lock + * CPUB acquires host lock + * CPUB posts write of index 6 to mailbox4 + * On PCI bus, order reverses and write of 6 posts, then index 5, + * causing chip to issue full queue of stale commands + * The mmiowb() prevents future writes from crossing the barrier. + * See Documentation/DocBook/deviceiobook.tmpl for more information. + */ WRT_REG_WORD(®->mailbox4, ha->req_ring_index); - (void) RD_REG_WORD(®->mailbox4); /* PCI posted write flush */ + mmiowb(); LEAVE("qla1280_isp_cmd"); } - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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