[lkml]   [2004]   [Aug]   [6]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: [PATCH] x86 bitops.h commentary on instruction reordering
    Followup to:  <20040806170931.GA21683@logos.cnet>
    By author: Marcelo Tosatti <>
    In newsgroup:
    > > >
    > > >Yes correct. *mb() usually imply barrier().
    > > >
    > > >About the flush, each architecture defines its own instruction for doing
    > > >so,
    > > > PowerPC has "sync" and "isync" instructions (to flush the whole cache
    > > > and instruction cache respectively), MIPS has "sync" and so on..
    > >
    > > So, there is no platform independent way for doing that in the kernel?
    > Not really. x86 doesnt have such an instruction.

    Actually it does (sfence, lfence, mfence); they only apply to SSE
    loads and stores since all other x86 operations are guaranteed to be
    strictly ordered.


    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    More majordomo info at
    Please read the FAQ at

     \ /
      Last update: 2005-03-22 14:05    [W:0.019 / U:131.016 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site