lkml.org 
[lkml]   [2004]   [Aug]   [6]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    From
    SubjectRe: [PATCH] x86 bitops.h commentary on instruction reordering
    Date
    Followup to:  <20040806170931.GA21683@logos.cnet>
    By author: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
    In newsgroup: linux.dev.kernel
    > > >
    > > >Yes correct. *mb() usually imply barrier().
    > > >
    > > >About the flush, each architecture defines its own instruction for doing
    > > >so,
    > > > PowerPC has "sync" and "isync" instructions (to flush the whole cache
    > > > and instruction cache respectively), MIPS has "sync" and so on..
    > >
    > > So, there is no platform independent way for doing that in the kernel?
    >
    > Not really. x86 doesnt have such an instruction.
    >

    Actually it does (sfence, lfence, mfence); they only apply to SSE
    loads and stores since all other x86 operations are guaranteed to be
    strictly ordered.

    -hpa


    -
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to majordomo@vger.kernel.org
    More majordomo info at http://vger.kernel.org/majordomo-info.html
    Please read the FAQ at http://www.tux.org/lkml/

    \
     
     \ /
      Last update: 2005-03-22 14:05    [W:0.022 / U:0.124 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site