Messages in this thread | | | Date | Fri, 6 Aug 2004 14:09:31 -0300 | From | Marcelo Tosatti <> | Subject | Re: [PATCH] x86 bitops.h commentary on instruction reordering |
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On Fri, Aug 06, 2004 at 08:52:34PM +0400, Vladislav Bolkhovitin wrote: > Marcelo Tosatti wrote: > >On Fri, Aug 06, 2004 at 07:36:25PM +0400, Vladislav Bolkhovitin wrote: > > > >>Thanks. > >> > >>One more question, if you don't object. How after some variable > >>assigment to make other CPUs *immediatelly* see the assigned value, i.e. > >>to make current CPU immediately flush its write cache in memory? *mb() > >>seems deal with reordering, barrier() with the compiler optimization (am > >>I right?). > > > > > >Yes correct. *mb() usually imply barrier(). > > > >About the flush, each architecture defines its own instruction for doing > >so, > > PowerPC has "sync" and "isync" instructions (to flush the whole cache > > and instruction cache respectively), MIPS has "sync" and so on.. > > So, there is no platform independent way for doing that in the kernel?
Not really. x86 doesnt have such an instruction. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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