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SubjectRe: [patch] voluntary-preempt-2.6.8.1-P2

* Thomas Charbonnel <thomas@undata.org> wrote:

> The next problem I have relates to irq sharing.
> On my laptop I can't avoid it :
> 10: 1070631 XT-PIC yenta, yenta, uhci_hcd, Intel
> 82801CA-ICH3, hdsp, eth0
> If I set the sound card's interrupt to be non threaded, then I get a
> rather long non preemptible section :
> http://www.undata.org/~thomas/irq_sharing.trace

i'm not sure the IRQ sharing problem can be solved.

we could execute certain handlers immediately, and defer others to an
IRQ thread. But when we defer an IRQ we must keep the IRQ masked - which
prevents further interrupts (possibly from a high-prio non-threaded
handler) to be executed. So we'd see similar (or in fact worse, due to
the redirection cost) latencies than with the current 'all or nothing'
approach.

now in theory we only have to keep the IRQ line masked for level
triggered interrupts (most APIC interrupts are level-triggered).
Edge-triggered interrupts (such as the XT-PIC ones you have) could be
acked immediately. I'll try to do something later, but right now there
are still some IRQ problems (USB issues, PS2 mouse/keyboard issues) so
i'd not like to complicate the design just yet.

Ingo
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