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SubjectRe: DMA API issues
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> +-----+
> | CPU |
> +--+--+
> |
> <-----+-----+----------------------+-----> Central Bus
> | |
> +-----+------+ +------+-----+
> | Memory | | I/O |
> | Controller | | Controller |
> +-----+------+ +------+-----+
> | |
> +---+-----+ +--+---+ +--------+
> | Memory | | OHCI |----| Memory |
> +---------+ +------+ +--------+
> In order to access this OHCI memory, both the I/O controller and the
> OHCI have to respond to the memory access cycles, rather than the memory
> controller. This is why such memory is termed "bus remote".

Why in an abstract API would we care how the memory is connected to
the system? Isn't the only relevant issue whether the memory is in the
CPU's normal address space?

> Even though ARM can programm the I/O controller and the OHCI device to
> access this memory as though it were behind the memory controller (i.e.
> using normal CPU memory cycles), you'll find that even on ARM there's
> probably special page table trickery involved (probably to do with cache
> coherency issues). Next, you'll find that no other device can see this
> memory without some type of i2o support, so it can't be the target of a
> DMA transaction. So even on ARM, you can't treat it as "normal" memory.

How is it relevant whether memory can be DMAed to by devices other
than the device in question? Even on regular x86 there's the low 16MB,
isn't there?

> The DMA API is about allowing devices to transact directly with memory
> behind the memory controller, it's an API that essentially allows the
> I/O controller and memory controller to communicate without CPU
> intervention. This is still possible through the hypervisor, so the
> iSeries currently fully implements the DMA API.

Then what's the problem?

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