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SubjectRE: PATCH: Further aacraid work
Using the 32 bit dma descriptors was used to optimize the transfer size
and performance. There is a small performance hit by switching to a
resultant larger FIB (adapter command packet) with 64 bit SG elements,
and an accompanied reduced limit on the number of total SG elements
available. Since the scsi layer has a propensity to provide sequentially
decreasing pages (sequentially increasing would permit coalescing of SG
elements) for the SG elements, we find that there is an average SG
element size of 4K.

The performance hit is up to 15% when the request has to be split to fit
into the available SG element slots.

An increase in performance of the scsi layer could occur if the
allocator provided sequentially increasing pages to permit a larger SG
element to be sent down to the adapter, and thus a larger request down
to the adapter.

I *must* admit that the driver functions perfectly in other systems with
more than 4G of memory; however we *are* having troubles specifically
with AMD64 systems with more than 4G of memory in 2.6 kernels (the issue
does not occur on 2.4 kernels). I have yet to investigate why this
specific problem exists.

One would expect that if we erroneously got the memory model wrong (ie,
<4GB of memory, one slice at 0-2G, another slice at 4G-6G) that the 32
dma limit would protect us from functional problems in this delicate
area but with a performance hit resulting from the scsi layer providing
bounce buffers. Ideally we would like to have a mechanism to know if the
DMAable area is limited to a 32 bit address space in order to take
advantage of the more efficient FIB utilization.

Sincerely -- Mark Salyzyn

-----Original Message-----
[] On Behalf Of Alan Cox
Sent: Wednesday, June 16, 2004 6:06 PM
To: Christoph Hellwig; Alan Cox;;
Subject: Re: PATCH: Further aacraid work

On Wed, Jun 16, 2004 at 10:58:34PM +0100, Christoph Hellwig wrote:
> Yikes. This looked like they usual use 32bit dma descriptors if not
> enough memory hacks to me. If aacraid is that royally fucked we
> probably add CONFIG_X86 to it.

Its working on x86-32, x86-64 and I believe (Mark can confirm this)
I'm fairly sure there are some platforms that aren't going to fit the
hardware's view of the world which seems to be

0[DMAable area..................]defined limit [4Gb+.. PAE mode on

The later cards also have a 2Gb limit for the ring buffers, but not for
I/O you want to target

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