Messages in this thread | | | Date | Wed, 5 May 2004 15:31:02 -0700 | From | Greg KH <> | Subject | Re: PCI devices with no PCI_CACHE_LINE_SIZE implemented |
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On Thu, Apr 29, 2004 at 02:53:01PM -0500, Matt Domsch wrote: > Greg, > > Some PCI device functions, such as the EHCI portion of Intel ICH5 and > ICH6 chips, do not implement the PCI_CACHE_LINE_SIZE register (which > is legal to not implement per PCI spec as it is a busmaster that > cannot issue a MWI). However, for each of these, the kernel tries to > set the value, fails, and prints a KERN_WARNING message about it. > > a) need this be a warning, wouldn't KERN_DEBUG suffice, if a message > is needed at all? This is printed in pci_generic_prep_mwi().
Yes, we should make that KERN_DEBUG. I don't have a problem with that. Care to make a patch?
> b) How might you prefer to handle such devices? > > Per the PCI 2.3 spec, reading a value of 0 may mean several things: > 1) setting the register at all isn't supported > - this is what pci.c assumes now and returns -EINVAL. > 2) setting the register to the value you tried isn't supported, but > you can try again with another value until you find the right one. > - but there are no hints as to what the right value for a device > might be.
I think we need to stick with 1, unless we get more info on what the "proper" value should be.
thanks,
greg k-h - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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