lkml.org 
[lkml]   [2004]   [May]   [23]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: 2.6.6-mm5
From
Date
Andi Kleen <ak@muc.de> writes:

> ebiederm@xmission.com (Eric W. Biederman) writes:
>
> > Currently I know of a safe version that will work on x86 on processors
> > with sse support. And I how to generate 64bit I/O cycles with using
> > mmx or x87 registers, but don't know if I can write code that touches
> > the FPU registers that is interrupt safe.
>
> As long as you save/restore cr0 and the FPU registers and do clts
> interrupts are not a problem. In fact interrupts are even easier that
> process context, where you need preempt_disable().

The saving and restoring is where things are looking icky.

It does not look like that kernel_fpu_begin() will work safely in
an interrupt context.

The generic x86 variant is to do:

fild
fistp

Which works for 64bit values because the floating point registers
have a 64bit mantissa.

I suppose I could unconditionally save the x87 floating point registers
to a local variable, but that sounds like a terribly expensive operation.
At least with kernel_fpu_begin() the floating point save only
needs to happen once, per context switch.

With SSE it is easy to save just a single register. For the x87 I don't
see how to do that. Beyond the stack based nature of the x87 there is
the question if the registers are in mmx mode or not.

I guess a conservative always correct version would be a place to start.

Eric
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 14:03    [from the cache]
©2003-2014 Jasper Spaans. Advertise on this site