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SubjectRe: drivers/char/dz.[ch]: reason for keeping?
On Wed, 7 Apr 2004, Jan-Benedict Glaw wrote:

> - Separate RX and TX interrupt. This part is tricky because on
> VAX, the triggered IRQ needs to be ACKed twice. On the CPU and
> on the vsbus controller, as it seems. That is, both VAX IRQ
> handlers explicitely ACK their respective vsbus IRQ.

But this is done by the platform-specific IRQ controller handler -- the
driver is not aware of the setup used. For example on the DECstation
interrupts arriving from the TURBOchannel, depending on the system, may
come through three kinds of IRQ controllers, for which the following
handlers are used: kn02_irq_type, ioasic_irq_type and
mips_cpu_irq_controller (hmm, the latter should probably be renamed for
consistency). None of the TC drivers cares.

> - Register offsets are offset_mips = offset_vax * 2.

Yes, and this essentially means we want configuration-specific read and
write backends. For the Alpha the rule could be yet different. Note the
driver now incorrectly operates directly on virtual addresses, while it
should use physical ones and obtain a virtual mapping as appropriate.

> I'm not that familiar with the TC busses. Do you have the same register
> offsets on the TC chips compared to the onboard DZ11? (So are
> register offsets machine specific or bus specific?)

I can't recall TC wiring off the head. Certainly the offsets may be
different as they depend on how the address decoders are set up. I
suspect registers are word-aligned as the TC has a 32-bit data path.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
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