[lkml]   [2004]   [Apr]   [22]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: IO-APIC on nforce2 [PATCH]
On Thu, 22 Apr 2004, Len Brown wrote:

> So if
> 1. all nforce2 chipsets have timer connected to pin0

Allen, is there a possibility to get a clarification from Nvidia on that?
Specifically, assuming both an 8254 and an I/O APIC core are integrated
into the chip, whether OUT0 of the 8254 is unconditionally routed to
INTIN0 of the I/O APIC or is it configurable somehow.

> 2. we can safely discover we're on nforce2 early enough,
> like andi did on x86_64
> then we could apply the workaround automatically always
> w/o any harm.


+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+ e-mail:, PGP key available +
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

 \ /
  Last update: 2005-03-22 14:02    [W:0.082 / U:8.540 seconds]
©2003-2017 Jasper Spaans. hosted at Digital OceanAdvertise on this site