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On Thu, 22 Apr 2004, Len Brown wrote: > So if> 1. all nforce2 chipsets have timer connected to pin0 Allen, is there a possibility to get a clarification from Nvidia on that? Specifically, assuming both an 8254 and an I/O APIC core are integrated into the chip, whether OUT0 of the 8254 is unconditionally routed to INTIN0 of the I/O APIC or is it configurable somehow. > 2. we can safely discover we're on nforce2 early enough, > like andi did on x86_64 > > then we could apply the workaround automatically always > w/o any harm. Indeed. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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