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SubjectRe: want to clarify powerpc assembly conventions in head.S and entry.S
Date

>> stwcx. r0,0,r1 /* to clear the reservation */
>>
>> I don't see the corresponding lwarx instruction. What reservation is
>> it
>> referring to?
>
> This is to clear any possible pending reservation if any. The problem
> is
> that the reservation mecanism only works accross multiple CPUs. A
> normal
> store at an address covered by a reservation on the same CPU will not
> break
> the reservation. Thus, to protect from that, any interrupt or exception
> makes sure to return to the normal code flow with any pending
> reservation
> cleared.

Worse, it is allowed for a PowerPC implementation to not check if
stwcx. and
stdcx. refer to the same address as the preceding lwarx or ldarx . So,
a store
conditional insn can succeed because the cpu holds some *other*
reservation.
Therefore, the kernel has to clear any reservation that might not have
been
generated by the user code it is returning to.


Segher


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