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Hi! > in your patch, you write> +/* Here is the PAT's default layout on ia32 cpus when we are done. > + * PAT0: Write Back> + * PAT1: Write Combine> + * PAT2: Uncached> + * PAT3: Uncacheable> + * PAT4: Write Through> + * PAT5: Write Protect> + * PAT6: Uncached> + * PAT7: Uncacheable> > Is that layout possible?> There is an errata in the B2 and C1 stepping of the Pentium 4 cpus > that results in incorrect PAT numbers: the highest bit is ignored by > the CPU under some circumstances. There's a similar errata (E27) that > affects all Pentium 3 cpus: The highest bit is always ignored. > I think we need a fallback to 4 PAT entries. What about arranging it so that foo is always more restrictive than foo|4? That way you can get some slowdowns on bad cpus, but it will always be correct. -- 64 bytes from 195.113.31.123: icmp_seq=28 ttl=51 time=448769.1 ms - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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