Messages in this thread | | | Date | Wed, 11 Feb 2004 11:30:15 -0800 | From | "David S. Miller" <> | Subject | Re: [Patch] dma_sync_to_device |
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On Wed, 11 Feb 2004 12:23:19 -0700 Matt Porter <mporter@kernel.crashing.org> wrote:
> On Wed, Feb 11, 2004 at 10:30:56AM -0800, David S. Miller wrote: > > 1) pci_map_single(), device DMA's from the buffer. > > > > 2) pci_dma_sync_single(). Cpu writes some new command or > > status flag into the buffer. > > > > 3) pci_dma_sync_to_device_single(), now device is asked to DMA from the buffer > > again. > > Actually, not yet. Is it not possible for MIPS to determine the correct > cache operation to use if step #3 used a pci_dma_sync_single() with a > TO_DEVICE direction?
It should do a writeback of dirty data from the cpu cache, so that the device may see it after pci_dma_sync_to_device_single() completes.
> I'm guessing that MIPS must have some kind of bridge cache in order to > require the pci_dma_sync_to_device_single() if I'm starting to follow > this.
Some platforms do, some don't. Sparc64 has PCI controller DMA caches but it's cpu caches are fully coherent, for example. On such a platform this new interface is going to be a NOP, but on things like MIPS it will not be.
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