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Benjamin Herrenschmidt wrote: > They may not end up in order if they are stores (the stores to the > taskfile may be out of order vs; the loads/stores to/from the data > register) unless you have a spinlock protecting both or a full sync (on > ppc), but then, I don't know the ordering things on x86_64. This could > certainly be a problem on ppc & ppc64 too. Is synchronization beyond in[bwl] needed, do you think? This specific problem is only on Intel ICHx AFAICS, which is PIO not MMIO and x86-only. I presumed insw() by its very nature already has synchronization, but perhaps not... Jeff - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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