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    Subjectpage fault scalability patch V11 [3/7]: ia64 atomic pte operations
    Changelog
    * Provide atomic pte operations for ia64
    * Enhanced parallelism in page fault handler if applied together
    with the generic patch

    Signed-off-by: Christoph Lameter <clameter@sgi.com>

    Index: linux-2.6.9/include/asm-ia64/pgalloc.h
    ===================================================================
    --- linux-2.6.9.orig/include/asm-ia64/pgalloc.h 2004-10-18 14:53:06.000000000 -0700
    +++ linux-2.6.9/include/asm-ia64/pgalloc.h 2004-11-19 07:54:19.000000000 -0800
    @@ -34,6 +34,10 @@
    #define pmd_quicklist (local_cpu_data->pmd_quick)
    #define pgtable_cache_size (local_cpu_data->pgtable_cache_sz)

    +/* Empty entries of PMD and PGD */
    +#define PMD_NONE 0
    +#define PGD_NONE 0
    +
    static inline pgd_t*
    pgd_alloc_one_fast (struct mm_struct *mm)
    {
    @@ -78,12 +82,19 @@
    preempt_enable();
    }

    +
    static inline void
    pgd_populate (struct mm_struct *mm, pgd_t *pgd_entry, pmd_t *pmd)
    {
    pgd_val(*pgd_entry) = __pa(pmd);
    }

    +/* Atomic populate */
    +static inline int
    +pgd_test_and_populate (struct mm_struct *mm, pgd_t *pgd_entry, pmd_t *pmd)
    +{
    + return ia64_cmpxchg8_acq(pgd_entry,__pa(pmd), PGD_NONE) == PGD_NONE;
    +}

    static inline pmd_t*
    pmd_alloc_one_fast (struct mm_struct *mm, unsigned long addr)
    @@ -132,6 +143,13 @@
    pmd_val(*pmd_entry) = page_to_phys(pte);
    }

    +/* Atomic populate */
    +static inline int
    +pmd_test_and_populate (struct mm_struct *mm, pmd_t *pmd_entry, struct page *pte)
    +{
    + return ia64_cmpxchg8_acq(pmd_entry, page_to_phys(pte), PMD_NONE) == PMD_NONE;
    +}
    +
    static inline void
    pmd_populate_kernel (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte)
    {
    Index: linux-2.6.9/include/asm-ia64/pgtable.h
    ===================================================================
    --- linux-2.6.9.orig/include/asm-ia64/pgtable.h 2004-11-15 11:13:38.000000000 -0800
    +++ linux-2.6.9/include/asm-ia64/pgtable.h 2004-11-19 07:55:35.000000000 -0800
    @@ -414,6 +425,26 @@
    #endif
    }

    +/*
    + * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
    + * information. However, we use this routine to take care of any (delayed) i-cache
    + * flushing that may be necessary.
    + */
    +extern void update_mmu_cache (struct vm_area_struct *vma, unsigned long vaddr, pte_t pte);
    +
    +static inline int
    +ptep_cmpxchg (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, pte_t oldval, pte_t newval)
    +{
    + /*
    + * IA64 defers icache flushes. If the new pte is executable we may
    + * have to flush the icache to insure cache coherency immediately
    + * after the cmpxchg.
    + */
    + if (pte_exec(newval))
    + update_mmu_cache(vma, addr, newval);
    + return ia64_cmpxchg8_acq(&ptep->pte, newval.pte, oldval.pte) == oldval.pte;
    +}
    +
    static inline int
    pte_same (pte_t a, pte_t b)
    {
    @@ -476,13 +507,6 @@
    struct vm_area_struct * prev, unsigned long start, unsigned long end);
    #endif

    -/*
    - * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
    - * information. However, we use this routine to take care of any (delayed) i-cache
    - * flushing that may be necessary.
    - */
    -extern void update_mmu_cache (struct vm_area_struct *vma, unsigned long vaddr, pte_t pte);
    -
    #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
    /*
    * Update PTEP with ENTRY, which is guaranteed to be a less
    @@ -560,6 +584,8 @@
    #define __HAVE_ARCH_PTEP_MKDIRTY
    #define __HAVE_ARCH_PTE_SAME
    #define __HAVE_ARCH_PGD_OFFSET_GATE
    +#define __HAVE_ARCH_ATOMIC_TABLE_OPS
    +#define __HAVE_ARCH_LOCK_TABLE_OPS
    #include <asm-generic/pgtable.h>

    #endif /* _ASM_IA64_PGTABLE_H */
    -
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