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    SubjectRe: [patch] Real-Time Preemption, -RT-2.6.10-rc1-mm3-V0.7.25-1
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    On Fri, 2004-11-12 at 15:13, Ingo Molnar wrote:
    > * Shane Shrybman <shrybman@aei.ca> wrote:
    >
    > > V0.7.25-1 has been stable here with the ivtv driver for 11 hrs. No
    > > sign of the ide dma time out issue either. Out of curiosity, do we
    > > know what solved that problem?
    >
    > could you try the attached patch - does it trigger the DMA timeouts
    > again? There were 3 changes to the IOAPIC code that could have affected
    > your dma-timeout problem, this patch reverts all of them.
    >

    Yes it does trigger the DMA timeouts again. Just the addition of
    CONFIG_SMP dep is enough to trigger it. Which isn't surprising since
    the hack was to put #if 0 there wasn't it?

    > Mark's suggestion sounds quite plausible too - but the question is, your
    > timeout problems went away previously by tweaking io_apic.c, so it would
    > be nice to see that they are still gone even with the old 'broken'
    > io_apic.c logic. (none of the io_apic.c changes fixes any particular
    > bug, they are only latency optimizations, so i'd be surprised if they
    > really impacted your timeout problems.)
    >
    > if the DMA timeouts are still gone even with this patch applied then i
    > think it's safe to conclude that Mark's explanation is the correct one,
    > and that it was starvation of the SCHED_OTHER IDE irq-thread that caused
    > the timeouts: it _really_ was a timeout. (a workaround would be to make
    > the timeout longer)
    >
    > Ingo
    >
    > --- linux/arch/i386/kernel/io_apic.c.orig2
    > +++ linux/arch/i386/kernel/io_apic.c
    > @@ -150,7 +150,7 @@ static void update_io_apic_cache(unsigne
    > }
    > }
    >
    > -#define IOAPIC_CACHE
    > +// #define IOAPIC_CACHE
    > /*
    > * Some systems need a POST flush or else level-triggered interrupts
    > * generate lots of spurious interrupts due to the POST-ed write not
    > @@ -188,7 +188,7 @@ static void __modify_IO_APIC_irq (unsign
    > /*
    > * Force POST flush by reading:
    > */
    > - reg = *(IO_APIC_BASE(entry->apic)+4);
    > + reg = io_apic_read(entry->apic, 0x10 + pin*2);
    > #endif
    > if (!entry->next)
    > break;
    > @@ -1940,7 +1940,7 @@ static unsigned int startup_level_ioapic
    > * unacked local APIC is dangerous on SMP as it can prevent the
    > * delivery of IPIs and can thus cause deadlocks.)
    > */
    > -#if defined(CONFIG_PREEMPT_HARDIRQS) && defined(CONFIG_SMP)
    > +#if defined(CONFIG_PREEMPT_HARDIRQS)
    >
    > static void mask_and_ack_level_ioapic_irq(unsigned int irq)
    > {
    >

    shane

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