Messages in this thread | | | Subject | Re: [PATCH] I/O space write barrier | From | Benjamin Herrenschmidt <> | Date | Wed, 06 Oct 2004 08:41:40 +1000 |
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On Wed, 2004-10-06 at 01:33, Jesse Barnes wrote:
> This macro is only supposed to deal with writes from different CPUs that may > arrive out of order, nothing else. It sounds like PPC won't allow that > normally, so I can be an empty definition.
I don't understand that neither. You can never guarantee any ordering between writes from different CPUs unless you have a sinlock. If you have an ordering problem with spinlocks, then it's a totally different issue, a bit more like MMIO vs. cacheable mem that we have on PPC. If this is the problem you are trying to chase, then we could use such a barrier on ppc too and make it a hard sync, but it has nothing to do with the write barrier we already have in our IO accessors...
> > That doesn't solve my need of MMIO vs. memory unless you are trying to > > cover that as well, in which case it should be a sync. > > No, I think that has to be covered separately.
How so ? Again, this whole "ordering of writes between different CPU" makes absolutely no sense to me.
Ben.
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