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    Subject[PATCH] use mmiowb in qla1280.c
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    There are a few spots in qla1280.c that don't need a full PCI write flush to 
    the device, but rather a simple write ordering guarantee. This patch changes
    some of the PIO reads that cause write flushes into mmiowb calls instead,
    which is a lighter weight way of ensuring ordering.

    Jes and James, can you ack this and/or push it in via the SCSI BK tree?

    Thanks,
    Jesse

    Signed-off-by: Jeremy Higdon <jeremy@sgi.com>
    Signed-off-by: Jesse Barnes <jbarnes@sgi.com>


    ===== drivers/scsi/qla1280.c 1.69 vs edited =====
    --- 1.69/drivers/scsi/qla1280.c 2004-10-20 06:46:21 -07:00
    +++ edited/drivers/scsi/qla1280.c 2004-10-21 16:06:11 -07:00
    @@ -3400,7 +3400,8 @@
    sp->flags |= SRB_SENT;
    ha->actthreads++;
    WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
    - (void) RD_REG_WORD(&reg->mailbox4); /* PCI posted write flush */
    + /* Enforce mmio write ordering; see comment in qla1280_isp_cmd(). */
    + mmiowb();

    out:
    if (status)
    @@ -3668,7 +3669,8 @@
    sp->flags |= SRB_SENT;
    ha->actthreads++;
    WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
    - (void) RD_REG_WORD(&reg->mailbox4); /* PCI posted write flush */
    + /* Enforce mmio write ordering; see comment in qla1280_isp_cmd(). */
    + mmiowb();

    out:
    if (status)
    @@ -3778,9 +3780,21 @@
    } else
    ha->request_ring_ptr++;

    - /* Set chip new ring index. */
    + /*
    + * Update request index to mailbox4 (Request Queue In).
    + * The mmiowb() ensures that this write is ordered with writes by other
    + * CPUs. Without the mmiowb(), it is possible for the following:
    + * CPUA posts write of index 5 to mailbox4
    + * CPUA releases host lock
    + * CPUB acquires host lock
    + * CPUB posts write of index 6 to mailbox4
    + * On PCI bus, order reverses and write of 6 posts, then index 5,
    + * causing chip to issue full queue of stale commands
    + * The mmiowb() prevents future writes from crossing the barrier.
    + * See Documentation/DocBook/deviceiobook.tmpl for more information.
    + */
    WRT_REG_WORD(&reg->mailbox4, ha->req_ring_index);
    - (void) RD_REG_WORD(&reg->mailbox4); /* PCI posted write flush */
    + mmiowb();

    LEAVE("qla1280_isp_cmd");
    }
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