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SubjectRe: [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT
On Sun, Sep 07, 2003 at 10:30:52PM +0200, Andi Kleen wrote:
> Adrian Bunk <bunk@fs.tum.de> writes:
>
> > With CONFIG_M686 CONFIG_X86_L1_CACHE_SHIFT was set to 5, but a Pentium 4
> > requires 7.
> It doesn't require 7, it just prefers 7.

*nod*. This 'fix' also papers over the bug instead of fixing it.
Likely it's something like a network card driver setting its cacheline
size incorrectly. Peter what NIC did you see the problem on ?

I thought Ivan's PCI cacheline sizing fixes from 2.6
(see arch/i386/pci/common.c) already made it into 2.4,
but from a quick grep, it seems that didn't happen.

> > The patch below does:
> > - set CONFIG_X86_L1_CACHE_SHIFT 7 for all Intel processors (needed for
> > the Pentium 4)
> > - set CONFIG_X86_L1_CACHE_SHIFT 6 for the K6 (needed for the Athlon)
> I think these changes should be only done with CONFIG_X86_GENERIC is set.
> Otherwise the people who want kernels really optimized for their CPUs
> won't get the full benefit. On UP it does not make that much difference,
> but on a SMP kernel having a bigger than needed cache size wastes a lot
> of memory.

ACK.

Dave

--
Dave Jones http://www.codemonkey.org.uk
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