Messages in this thread | | | From | "Luca Veraldi" <> | Subject | Re: Efficient IPC mechanism on Linux | Date | Wed, 10 Sep 2003 12:17:13 +0200 |
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> This test is sort of the worst case against my argument: > 1) It's a cpu with low memory bandwidth > 2) It's a 1 CPU system > 3) It's a pII not pIV; the pII is way more efficient cycle wise > for pagetable operations
I'm a Compuer Science graduate. And at least one single thing I've learned in my studies. More efficient Firmware support (such as an extremely wide memory bandwith or tens of CPUs in an SMP/NUMA or efficient cache line transfer support)
DOES NOT ALLOW YOU TO WASTE CYCLES IN DOING USELESS THINGS, such as TWO physical copies of a message if a process want to cooperate with another one.
We are not engineer that simply have to let the things work.
That's all. Luca.
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