Messages in this thread | | | Date | Mon, 1 Sep 2003 05:49:23 +0100 | From | Jamie Lokier <> | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this |
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J.A. Magallon wrote: > On 08.29, Jamie Lokier wrote: > > I already got a surprise (to me): my Athlon MP is much slower > > accessing multiple mappings which are within 32k of each other, than > > mappings which are further apart, although it is coherent. The L1 > > data cache is 64k. (The explanation is easy: virtually indexed, > > physically tagged cache moves data among cache lines, possibly via L2). > > > > Sorry if this is a stupid question, but have you heard about 64K-aliasing ? > We have seen it in P3/P4, do not know if Athlons also suffer it. > In short, x86 is crap. It slows like a dog when accessing two memory > positions sparated by 2^n (address decoder has two 16 bits adders, instead > of 1 32 bits..., cache is 16 bit tagged, etc...)
I don't know what you mean. This test doesn't observe any gross timing effect at 64K. I have just tried it on a Celeron Coppermine printing more detailed numbers, and I don't notice anything at all.
So, what exactly do you mean? What kind of code shows the effect you are talking about?
Thanks, -- Jamie - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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