Messages in this thread | | | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this | From | Alan Cox <> | Date | Mon, 01 Sep 2003 12:17:03 +0100 |
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On Llu, 2003-09-01 at 07:00, Jamie Lokier wrote: > Matt Porter wrote: > > PPC440GX, non cache coherent, L1 icache is VTPI, L1 dcache is PTPI > > The cache looks very coherent to me.
The only x86 which will show the user non cache coherent behaviour (and then only in a really weird situation) is SMP Pentium Pro due to the store fence errata.
The Winchip is non SMP so you won't see CPU<->CPU store ordering changes although I guess mmap of mmio space might show you stuff if you really tried hard
The Geode has bus level magic so its out of order but if you ask then you get the right answer (kind of the zen question about falling trees implemented in silicon).
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