| | Date | Mon, 1 Sep 2003 07:00:40 +0100 | | From | Jamie Lokier <> | | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this |
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Matt Porter wrote: > PPC440GX, non cache coherent, L1 icache is VTPI, L1 dcache is PTPI
The cache looks very coherent to me.
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