Messages in this thread | | | Date | Mon, 26 May 2003 23:19:38 +0100 | From | Russell King <> | Subject | Re: [patch] cache flush bug in mm/filemap.c (all kernels >= 2.5.30(at least)) |
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On Mon, May 26, 2003 at 03:08:12PM +0200, Lothar Wassmann wrote: > No, its still there. But I seem to be unable to turn writealloc ON > anyway. I get:
Ok, this gets worrying since I haven't heard of the problem occuring with our write back caches before, neither can I reproduce it here. It also completely knocks out my reasoning for it occuring.
> |CPU: XScale-PXA250 [69052904] revision 4 (ARMv5TE) > |CPU: D undefined 5 cache > |CPU: I cache: 32768 bytes, associativity 32, 32 byte lines, 32 sets > |CPU: D cache: 32768 bytes, associativity 32, 32 byte lines, 32 sets > |Machine: KARO electronics PXA25x module > |Memory policy: ECC disabled, Data cache write back > no matter whether I specify 'cachepolicy=writeback', '...writealloc' > or no cachepolicy at all. > (This is because ARMv5TE is not recognized as an ARMv5 architecture and > PMD_SECT_WBWA is turned into PMD_SECT_WB in build_mem_type_table() > ('arch/arm/mm/mm-armv.c' line 304). > Another bug?) > Shouldn't it be: > @@ -295,12 +295,13 @@ > /* > * ARMv5 can use ECC memory. > */ > - if (cpu_arch == CPU_ARCH_ARMv5) { > + if (cpu_arch == CPU_ARCH_ARMv5 || cpu_arch == CPU_ARCH_ARMv5T || > + cpu_arch == CPU_ARCH_ARMv5TE) {
No - it should be cpu_arch >= CPU_ARCH_ARMv5. I seem to have been over- zealous about removing some currently unreleasable stuff here.
-- Russell King (rmk@arm.linux.org.uk) The developer of ARM Linux http://www.arm.linux.org.uk/personal/aboutme.html
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