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SubjectRe: Test Patch: 2.5.69 Interrupt Latency
On 15 May 2003, Paul Fulghum wrote:

> I think I found the key to this whole problem:
>
> Note:I mistakenly referred to the chipset as PIIX3
> in previous messages, in fact it is the PIIX4 (BX)
>
> The PIIX4 errata states that false resume indications
> can be generated if CLK48 is active during an
> overcondition indication (OC[1..0]).
>
> Sure enough, the USBPORTSC[12] registers constantly
> report a status of 0C80 which shows that both
> ports are showing overcurrent condition (which
> disables the associated port).
>
> My guess is that HP deliberately tied the OC[1..0]
> inputs active to force the ports to a disabled state.
>
> So checking for the case of both ports constantly
> in OC condition and disabled may be a reasonable
> way to either disable the controller altogether or
> at least not do the wakeup/suspend shuffle.
>
> Any comments?

That sounds like a believable explanation. My copy of the generic UHCI
specification does not include the OC port status bits. I'm guessing from
your mail they are either bit 10 or bit 11 of the PORTSC registers, can't
tell which. Maybe they are an Intel-specific addition? Or perhaps a more
recent version of the spec has more information -- the one I've got is 1.1
(March 1996).

Can you suggest a good way of detecting whether or not a controller is
part of a PIIX4 chipset, to indicate whether or not the OC bits are valid?
Maybe the PCI vendor and product codes will have that information? I'm
not sure it's safe to assume that any old host controller will have
meaningful values there; the spec just says "reserved" and doesn't
stipulate that they will always read as 0's.

Alan Stern

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