Messages in this thread | | | Date | Fri, 28 Mar 2003 01:42:17 +0000 | From | Dave Jones <> | Subject | Re: Compiling kernel2.4.21-pre5 with L1 L2 cache |
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On Tue, Mar 25, 2003 at 04:24:32PM -0800, Juan F. Camino wrote:
> I have compiled kernel 2.4.20 (patch-2.4.21-pre5) but it does not > detect L1 and L2 Cache for my Celeron. Would that be a bug? Or am I missing > something on my configuration? I am quite sure Celeron has L2 =128k and > L1 = 8kb > dmesg > CPU: Trace cache: 12K uops, L1 D cache: 8K
Your Celeron has a P4 core. The L1 icache is replaced with a tracecache. As reported, you also have an 8KB L1 dcache. The L2 isn't reported. Possibly its missing the ident that was added to .21pre6
Dave
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