Messages in this thread | | | Date | Fri, 26 Dec 2003 11:44:35 -0800 (PST) | From | Davide Libenzi <> | Subject | Re: Page aging broken in 2.6 |
| |
On Fri, 26 Dec 2003, Arjan van de Ven wrote:
> > > > And we never flush the TLB entry. > > > > > > I don't know if x86 (or other archs really using page tables) will > > > actually set the referenced bit again in the PTE if it's already set > > > in the TLB, if not, then x86 needs a flush too. > > > > x86 needs a flush_tlb_page(), yes. > > it does? Are you 100% sure ?
According to the Intel doc #24319202, section 3.7, it is OS responsibility to invalidate the TLB entry.
- Davide
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |