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Gabriel Paubert wrote: Gabriel, I verified with PCI-E designers, uncacheable memory relates to snoop/non-snoop, not to buffering in bridge. Bridge will still buffer writes. The only way to be sure data has arrived, is to perform read. Vladimir. >>>Further, PCI posting: a writeb() / writew() / writel() will not be >>>flushed immediately to the processor. The CPU and/or PCI bridge may >>>post (delay/combine) such writes. I do not think this is a desireable >>>effect, for PCI config register accesses. >>> >>> >>> >>Good point. Fixed. >> >> > >Here I'm somehwat lost. Writes to uncacheable RAM will be in program >order and never combined. The bridge itself should not post writes to >config space. So it's a matter of pushing the write to the processor >bus, a PCI read looks very heavy for this. Isn't there a more >lightweight solution ? > > Regards, > Gabriel > > > - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||
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