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SubjectRe: Catching NForce2 lockup with NMI watchdog
Having had cause to try and figure out all this, I vote for the following being 
included in the source somewhere...


bill davidsen wrote:
> In article <>,
> Maciej W. Rozycki <> wrote:
> | The I/O APIC NMI watchdog utilizes the property of being transparent to a
> | single IRQ source of a specially reconfigured 8259A PIC (the master one in
> | the IA32 PC architecture). There are more prerequisites that have to be
> | met and all indeed are for a 100% compatible PC as specified by the
> | Intel's Multiprocessor Specification.
> |
> | 1. The INT output of the master 8259A PIC has to be connected to the LINT0
> | (or LINTIN0; the name varies by implementations) inputs of all local APICs
> | in the system.
> |
> | 2a. The OUT0 output of the 8254 PIT (IOW the timer source) has to be
> | directly connected to the INTIN2 input of the first I/O APIC.
> |
> | 2b. Alternatively the INT output of the master 8259A PIC has to be
> | connected to the INTIN0 input of the first I/O APIC.
> |
> | 3. There must be no glue logic that would change logical properties of the
> | signal between the INT output of the master 8259A PIC and the respective
> | APIC interrupt inputs.
> |
> | In practice, assuming the MP IRQ routing information provided the BIOS has
> | been correct (which is not always the case), prerequisites #1 and #2 have
> | been met so far, but #3 has proved to be occasionally problematic.
> In practice many system seem to take a good bit of guessing and testing.
> I have an old P-II which only works with acpi=force and nmi_watchdog=2,
> for instance.
> It would be nice if there were a program which could poke at the
> hardware and suggest options which might work, as in eliminating the
> ones which can be determined not to work. Absent that trial and error
> rule, unfortunately.

George Anzinger
Preemption patch:

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