Messages in this thread | | | Date | Thu, 30 Jan 2003 11:54:12 -0800 (PST) | From | Davide Libenzi <> | Subject | Re: frlock and barrier discussion |
| |
> Attached is a test app - could someone try it? I don't have access to a SMP > system right now.
Try to put [g_val1, g_seq1] and [g_val2, g_seq2] on two different cache lines and run it on a SMP system using CPUs with a partitioned cache architecture. Even if you do an WMB on writer side, you might see a different order w/out an RMB on the reader side. This because the two cache lines might be committed to different partitions with different loads, and the latest ( in time order ) commit might see a fastest path due a lower traffic. An RMB on the reader side ( that is usually expensive ) wait for all CPUs's memory controllers to flush their stuff before resuming execution.
- Davide
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |