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    SubjectRe: Info: NAPI performance at "low" loads
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    On Wed, 2002-09-18 at 21:23, David S. Miller wrote:
    > The x86 processor has a well defined timing for executing inb
    > etc. instructions, the timing is fixed and is independant of the
    > speed of the PCI bus the device is on.

    Earth calling Dave Miller

    The inb timing depends on the PCI bus. If you want proof set a Matrox
    G400 into no pci retry mode, run a large X load at it and time some inbs
    you should be able to get to about 100 milliseconds for an inb to
    execute

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