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    SubjectRe: Info: NAPI performance at "low" loads
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       From: ebiederm@xmission.com (Eric W. Biederman)
    Date: 18 Sep 2002 11:27:34 -0600

    "David S. Miller" <davem@redhat.com> writes:

    > {in,out}{b,w,l}() operations have a fixed timing, therefore his
    > results doesn't sound that far off.
    ????

    I don't see why they should be. If it is a pci device the cost should
    the same as a pci memory I/O. The bus packets are the same. So things like
    increasing the pci bus speed should make it take less time.

    The x86 processor has a well defined timing for executing inb
    etc. instructions, the timing is fixed and is independant of the
    speed of the PCI bus the device is on.
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