Messages in this thread | | | Subject | Re: [PATCH] [RFC] [2.5 i386] GCC 3.1 -march support, PPRO_FENCE reduction, prefetch fixes and other CPU-related changes | From | Luca Barbieri <> | Date | 04 Aug 2002 17:43:23 +0200 |
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> is there really support for SSE prefetch in athlons _without_ SSE?! > I don't know but this seems wrong... Yes, according to <http://www.amd.com/products/cpg/athlon/techdocs/pdf/22466.pdf>. AMD added several intructions in Athlons including movntq, sfence and prefetchnta/t0/t1/t2. The last 4 instructions are what I call "SSE prefetch" (they could called MMXEXT prefetch instead, but it's not much better).
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