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On 4 Aug 2002, Alan Cox wrote: > On Sat, 2002-08-03 at 23:16, Bartlomiej Zolnierkiewicz wrote: > > Just rethough it. What if chipset is in compatibility mode? > > Like VIA with base addresses set to 0? > > If we found a register that was marked as unassigned with a size then we > would map it to a PCI address. That would go for BAR0-3 on any PCI IDE > device attached to the south bridge. > > What problems does that cause for the VIA stuff ? In compatibility mode IDE chipsets have IO at legacy ISA ports and PCI_BASE_ADDRESS0-3 are set to them or to zero (at least on VIA). And they can't be programmed to any other ports (unless native mode). I am just asking if it can cause some problems. -- Bartlomiej - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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