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    SubjectRE: hpt374 / BUG();
    Date
    > You have a system where it actually have the PLL already set and in
    > 66-clock base? You are the first person to ever hit this BUG().
    > I will need to work with HighPoint to finish the timing table.
    >
    > If you would have several device of various max transfer rate limits you
    > could attach without the driver being built it, it would give me a few
    > data point to verify if the table I have started is even close.

    My HPT374 controller works with the new 2.4.20-pre2-ac6 patch, running at
    ATA-66.
    /proc/ide/hpt366 shows only primary and secondary channel, so I guess thats
    why the hard drives on channel 3 and 4 is not working?


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    UAG

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