Messages in this thread | | | Date | Mon, 19 Aug 2002 11:21:21 -0700 (PDT) | From | Xuehua Chen <> | Subject | A question about cache coherence |
| |
Met a problem in my research. I run some code on a Xeon dual-processor machine. It seems to me that there is a cache coherence problem. As I am not so familiar to this topic, I would like to ask some experts about the following questions.
1. Do Xeon processors have hardware mechanisms to maintain cache coherence? 2. Does the SMP kernel handle the cache coherence problem 3. What should I do if both of them don't handle cache coherence.
Thanks.
Frank Samuel
__________________________________________________ Do You Yahoo!? HotJobs - Search Thousands of New Jobs http://www.hotjobs.com - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |