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Hi, Just a few simple questions for you PCI experts (please correct any wrong assumptions): Imagine we have a PCI card with 2 MMIO regions: prefetchable PR1 and non-prefetchable NPR2 (and we are not limited to Pentium-class machines). I understand writes to PR1 can be reordered, merged, and delayed. What should I do to flush the write buffers? I understand reading from PR1 would do. Would reading from NPR2 flush PR1 write buffers? Would writing to NPR2 flush them? Now NPR2, the non-prefetchable MMIO region. Is it possible that the writes there are reordered, merged and/or delayed (delayed = not making it to the PCI device when the writel() completes)? We have ioremap() and ioremap_nocache(). What is the exact difference between them? Would the ioremap_nocache() disable all A) read- and B) write-caching on a) prefetchable MMIO b) non-prefetchable MMIO ? Would the ioremap() enable A) read- and A) write-caching on a) prefetchable MMIO b) non-prefetchable MMIO ? Thank you. -- Krzysztof Halasa Network Administrator - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | ||||||||||||
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