Messages in this thread | | | Date | Tue, 11 Jun 2002 01:15:25 -0700 (PDT) | Subject | Re: PCI DMA to small buffers on cache-incoherent arch | From | "David S. Miller" <> |
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From: Oliver Neukum <oliver@neukum.name> Date: Tue, 11 Jun 2002 10:07:19 +0200
Are there really PCI controllers which have to physically write much more than is transfered ?
On sparc64 the cacheline size can be either 64 or 128 bytes. It's a bus characteristic, so we have to get at the PCI controller info. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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