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    SubjectRe: PCI DMA to small buffers on cache-incoherent arch
    On Mon, Jun 10, 2002 at 12:21:44PM -0700, Roland Dreier wrote:
    > >>>>> "Tom" == Tom Rini <> writes:
    > Tom> SMP_CACHE_BYTES is non-sensical on 4xx (and 8xx) since they
    > Tom> don't do SMP..
    > True but <asm/cache.h> defines it anyway...

    Right, to L1_CACHE_BYTES even. :) So we should probably use that

    > of course it would be no
    > problem to use L1_CACHE_BYTES and in fact that probably makes sense
    > because we're talking about PPC-only macros (other arches would have
    > their own definition).

    Well, ARM (whom we (PPC)) borrowed some ideas from will set it to
    L1_CACHE_BYTES too, from the sound of rmk. So it might even be
    consistent among the non coherent processors. :)

    Tom Rini (TR1265)
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