Messages in this thread | | | Date | Mon, 10 Jun 2002 11:07:40 -0700 | From | William Jhun <> | Subject | Re: PCI DMA to small buffers on cache-incoherent arch |
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On Sun, Jun 09, 2002 at 09:27:05PM -0700, David S. Miller wrote: > From: Paul Mackerras <paulus@samba.org> > Date: Sun, 9 Jun 2002 19:51:58 +1000 (EST) > > This is the problem scenario. Suppose we are doing DMA to a buffer B > and also independently accessing a variable X which is not part of B. > Suppose that X and the beginning of B are both in cache line C. > > I see what the problem is. Hmmm... > > I'm trying to specify this such that knowledge of cachelines and > whatnot don't escape the arch specific code, ho hum... Looks like > that isn't possible.
Perhaps provide macros in asm/pci.h that will:
- Take a buffer size and add an appropriate amount (one cache line for alignment and the remainder to fill out the last cache line) to be used for kmalloc(), etc, eg:
#define DMA_SIZE_ROUNDUP(size) \ ((size + 2*SMP_CACHE_BYTES - 1) & ~(SMP_CACHE_BYTES - 1))
- Take a buffer address (as returned from kmalloc() with the modified size from above) and round it up to a cacheline boundary, eg:
#define DMA_BUFFER_ALIGN(ptr) \ (((unsigned long)ptr + SMP_CACHE_BYTES - 1) & ~(SMP_CACHE_BYTES - 1))
These two, in conjunction, would provide a buffer that's aligned on a cacheline boundary and ends on a cacheline boundary. Kind of ugly, but would be sufficient and would hide the cacheline size specifics. Cache-coherent platforms would just returned the original argument.
Thanks, Will - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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